Thin decoupling capacitor for mounting under integrated circuit package
US5034850A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1990 |
| Grant date | Jul 23, 1991 |
| Priority date | — |
| Expiry date | Feb 12, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10689
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A rugged, highly reliable, leadless decoupling capacitor is provided which may be positioned between a circuit board and an integrated circuit package including, for example, a leaded surface mounted IC package or Pin Grid Array package. This decoupling capacitor is comprised of a rugged ceramic or like substrate having printed or otherwise applied thereon a very thin high capacitance layer made by thick or thin film processes which is sandwiched between two thin electrode layers. Conductive castellations extend from the electrode layers along the surface of the ceramic substrate for connection to the circuit board. Preferably, an electrically insulative protective layer encapsulates the capacitor. The dielectric layer preferably comprises a high dielectric glass/ceramic dielectric paste or dielectric sol-gel layer. The overall thickness of the decoupling capacitor may be less than 0.020 inch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.