Method for implementing grid-based crosscheck test structures and the structures resulting therefrom
US5037771A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 28, 1989 |
| Grant date | Aug 6, 1991 |
| Priority date | — |
| Expiry date | Nov 28, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for fashioning CrossCheck testing structures allow the testing of high density integrated circuit structures to be made in a space efficient manner. In one method, sense lines and probe lines are disposed in different layers perpendicular to one another and a diffusion line is overlaid in such a manner as to form a sense transistor. In another method, a pair of probe lines are routed between each pair of cells in a manner to form a sense transistor. In still another embodiment circuit layout requires no modification to the basic macrocell structure and a metal interconnection layer is used to couple sense transistors to individual cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.