"Method for reducing masking of errors when using a grid-based, ""cross-check"" test structure"
US5038349A · kind A · utility
4Cited by
9References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 25, 1989 |
| Grant date | Aug 6, 1991 |
| Priority date | — |
| Expiry date | Aug 25, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/277
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Several methods for reducing the occurrence of masking of errors when using "Cross-Check" integrated circuit testing arrays and data compression devices such as multiple input shift registers are disclosed. The methods reduce the probability that successive faults within the logic circuit nodes of the integrated circuit will cancel one another by insuring that signals from logically proximate circuit nodes are either not provided sequentially to the data compression circuitry or are provided in such a way as to store any given error in at least two different locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.