Soft error immune memory
US5043939A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 1989 |
| Grant date | Aug 27, 1991 |
| Priority date | — |
| Expiry date | Jun 15, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/416
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An alpha radiation immune integrated circuit memory cell has a pair of secondary transistors connected to cross-couple the primary transistors to form a flow, secondary storage node. The secondary transistors are biased to a standby current that, in combination with the parasitic capacitances in the new cell, establishes a time constant sufficient to maintain the state of the secondary nodes during an alpha hit on the primary nodes, so that alpha immunity is achieved without added capacitance. A write boost circuit increases the current in the secondary transistors during a write operation. A memory array is formed of rows of such cells with all of the secondary emitters of each row coupled to a common emitter standby current source. The individual row emitter standby current sources are coupled together through a balanced resistor network so that the excess secondary emitter current generated during a write operation in a selected row is distributed across the non-selected rows, thereby maintaining the total secondary emitter current constant for the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.