Semiconductor memory device
US5043947A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 1990 |
| Grant date | Aug 27, 1991 |
| Priority date | — |
| Expiry date | May 30, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is provided including a plurality of memory arrays and peripheral circuits. For example, in a dynamic RAM the peripheral circuitry will include row address decoders, column address decoders, sense amplifiers and main amplifiers disposed in such a manner as to correspond to the memory arrays, respectively. The desired row address decoders, column address decoders, sense amplifiers and main amplifiers are selectively operated in accordance with a common array selection signal generated on the basis of at least part of row address signals. Accordingly, only the row address decoders, column address decoders, sense amplifiers and main amplifiers corresponding to the memory array containing the designated memory cells are operated selectively in accordance with the common array selection signal. It is thus possible to reduce power consumption of the dynamic RAM and to simplify the structure of the peripheral circuits and wirings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.