Transistor fabrication method
US5045486A · kind A · utility
20Cited by
5References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1990 |
| Grant date | Sep 3, 1991 |
| Priority date | — |
| Expiry date | Jun 26, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a transistor is disclosed. Conventional fabrication techniques direct an ion implantation beam toward a substrate upon which a gate has already been formed. If the gate stack is too low relative to the incident beam energy, the dopant species may channel thorugh the gate stack, adversely affecting transistor performance. The present invention prevents channeling through this gate by covering the gate with a protective layer before ion implantation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.