Method of manufacturing a single transistor non-volatile, electrically alterable semiconductor memory device
US5045488A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 22, 1990 |
| Grant date | Sep 3, 1991 |
| Priority date | — |
| Expiry date | Jan 22, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/685
Abstract
A methd of making an electrically programmable and erasable memory device having a re-crystallized floating gate is disclosed. A substrate is first defined. A first layer of dielectric material is grown over the substrate. A layer of polysilicon or amorphous silicon is then deposited over the first layer. The layer of silicon is covered with a protective material and is annealed to form recrystallized silicon. A portion of the protective material is removed to define a floating gate region. Making oxide is grown on the floating gate region. The remainder of the protective material and the recrystallized silicon thereunder is removed. A second layer of dielectric material is formed over the floating gate and over the substrate, immediately adjacent to the floating gate. A control gate is patterned and formed. Source and drain regions are then defined in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.