Method for forming capacitor using FET process and structure formed by same
US5045966A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 17, 1990 |
| Grant date | Sep 3, 1991 |
| Priority date | — |
| Expiry date | Sep 17, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/212
Abstract
A polysilicon or equivalent plate, to be used as an upper plate of the capacitor, is first formed over an oxide layer grown on a substrate. The length of the upper plate is made shorter than gate lengths of MOS transistors formed with the same process so that, after dopants are deposited into exposed regions of the substrate on both sides of the plate in a manner identical to forming self-aligned source and drain regions of an MOS transistor, the dopants will side-diffuse during drive-in and the diffused regions will be closely separated or merged under the plate. The resulting capacitor structure has a more stable capacitance with varying V.sub.GS levels than MOS transistors merely connected and used as capacitors and has a lower series resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.