Process for forming high and low voltage CMOS transistors on a single integrated circuit chip

US5047358A · kind A · utility

Assignee

• DELCO ELECTRONICS CORPORATION · US

Inventors

• Walter K. Kosiak · Kokomo, US
• Douglas R. Schnabel · Kokomo, US
• Jonathan Mann · Quakertown, US
• Jack D. Parrish · Kokomo, US
• Paul R. Rowlands, III · Kokomo, US

Key dates

• Filing date: Mar 17, 1989
• Grant date: Sep 10, 1991
• Expiry date: Mar 17, 2009

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83

Abstract

A process for forming both low voltage CMOS transistors and high voltage CMOS transistors on a common integrated circuit chip uses a common implantation and drive-in step to form both the n-type well of each PMOS transistor and the n-type drain extension well of each lightly doped drain (LDD) NMOS transistor and a separate implant and drive-in to form the p-type drain extension well of each LDD PMOS transistor.