System for scan testing of logic circuit networks
US5047710A · kind A · utility
36Cited by
8References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 26, 1989 |
| Grant date | Sep 10, 1991 |
| Priority date | — |
| Expiry date | Jul 26, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The integrity of a circuit processing logic signals is verified by use of switching means, including pass transistors, which are selectively varied to provide different test circuit configurations for different modes of operation. The circuit operates in normal, scan, test and data receive modes. During normal operation, the logic signal from the primary circuit is passed directly through a logic test block without the shifting of data in the logic test block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.