Amorphous-silicon thin film transistor array substrate
US5047819A · kind A · utility
33Cited by
5References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 12, 1990 |
| Grant date | Sep 10, 1991 |
| Priority date | — |
| Expiry date | Jul 12, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A reverse staggered amorphous silicon thin film transistor array substrate includes an array of amorphous silicon thin film transistors, gate wiring interconnecting the gate electrodes of the amorphous silicon thin film transistors, and source wirings. The transistor array is provided on a thin film transistor array substrate. A protective insulation layer and an amorphous silicon layer having a greater width than the source wiring are provided under the source wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.