High speed numerical processor for performing a plurality of numeric functions
US5047973A · kind A · utility
6Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 26, 1989 |
| Grant date | Sep 10, 1991 |
| Priority date | — |
| Expiry date | Apr 26, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5355
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Division and square root calculations are performed using an operand routing circuit (16) for receiving an operand N, and operand D and a seed value S and directing the operands and seed value to a multiplier (38). Single multiplier (38) is configured into two arrays for calculating partial products of N and S and D and S. The results of multiplier (38) are transmitted through switching circuitry (20) or registers (48) (50) either to operand routing circuitry (16) or adder (44) depending on a convergence algorithm. The final result is rounded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.