Donald E. Steiss
41Patents
15h-index
41Co-inventors
81Inventor score
Filing activity: Apr 26, 1989 → Feb 9, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7360064B1 | Thread interleaving in a multithreaded embedded processor | Physics | 128 | Expired |
| US5850543A | Microprocessor with speculative instruction pipelining storing a speculative register value within branch target buffer for use in speculatively executing instructions after a return | Physics | 91 | Expired |
| US6266754A | Secure computing device including operating system stored in non-relocatable page of memory | Physics | 87 | Expired |
| US5913049A | Multi-stream complex instruction set microprocessor | Physics | 85 | Expired |
| US6539467B1 | Microprocessor with non-aligned memory access | Physics | 58 | Expired |
| US6009516A | Pipelined microprocessor with efficient self-modifying code detection and handling | Physics | 38 | Expired |
| US6148395A | Shared floating-point unit in a single chip multiprocessor | Physics | 27 | Expired |
| US7441101B1 | Thread-aware instruction fetching in a multithreaded embedded processor | Physics | 26 | Expired |
| US6571363B1 | Single event upset tolerant microprocessor architecture | Physics | 22 | Expired |
| US5961632A | Microprocessor with circuits, systems, and methods for selecting alternative pipeline instruction paths based on instruction leading codes | Physics | 19 | Expired |
| US6065113A | Circuits, systems, and methods for uniquely identifying a microprocessor at the instruction set level employing one-time programmable register | Physics | 17 | Expired |
| US7551617B2 | Multi-threaded packet processing architecture with global packet memory, packet recirculation, and coprocessor | Electricity | 16 | Expired |
| US7206922B1 | Instruction memory hierarchy for an embedded processor | Physics | 16 | Expired |
| US6405351B1 | System for verifying leaf-cell circuit properties | Physics | 16 | Expired |
| US5838908A | Device for having processors each having interface for transferring delivery units specifying direction and distance and operable to emulate plurality of field programmable gate arrays | Physics | 16 | Expired |
| US6442667B1 | Selectively powering X Y organized memory banks | Emerging Cross-Sectional Technologies | 15 | Expired |
| US5815420A | Microprocessor arithmetic logic unit using multiple number representations | Physics | 14 | Expired |
| US6385120B1 | Power-off state storage apparatus and method | Physics | 11 | Expired |
| US8156309B2 | Translation look-aside buffer with variable page sizes | Emerging Cross-Sectional Technologies | 9 | Active |
| US6061811A | Circuits, systems, and methods for external evaluation of microprocessor built-in self-test | Physics | 7 | Expired |
| US6781411B2 | Flip flop with reduced leakage current | Electricity | 7 | Expired |
| US5047973A | High speed numerical processor for performing a plurality of numeric functions | Physics | 6 | Expired |
| US6766440B1 | Microprocessor with conditional cross path stall to minimize CPU cycle time length | Physics | 6 | Expired |
| US7739426B1 | Descriptor transfer logic | Electricity | 5 | Active |
| US6895493B2 | System and method for processing data in an integrated circuit environment | Physics | 4 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.