Chapter mode selection apparatus for MOS memory
US5047989A · kind A · utility
21Cited by
4References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 1989 |
| Grant date | Sep 10, 1991 |
| Priority date | — |
| Expiry date | Mar 10, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An EPROM includes an on chip circuitry for selecting an alternative chapter mode addressing scheme. By utilizing the chapter addressing mode, a plurality of devices can be coupled in parallel, wherein each device is treated as a chapter of the total memory capacity. Hard latches are used to store a designated code and soft latches are used to latch in chapter addresses from data lines. A chapter is evaluated if values stored in the hard latch match the values inputted to the soft latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.