Mark E. Bauer
32Patents
21h-index
37Co-inventors
85Inventor score
Filing activity: Mar 10, 1978 → Jul 31, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5539690A | Write verify schemes for flash memory with multilevel cells | Physics | 214 | Expired |
| US5523972A | Method and apparatus for verifying the programming of multi-level flash EEPROM memory | Physics | 202 | Expired |
| US5508958A | Method and apparatus for sensing the state of floating gate memory cells by applying a variable gate voltage | Physics | 197 | Expired |
| US5822256A | Method and circuitry for usage of partially functional nonvolatile memory | Physics | 165 | Expired |
| US5485422A | Drain bias multiplexing for multiple bit flash cell | Physics | 153 | Expired |
| US5475693A | Error management processes for flash EEPROM memory arrays | Physics | 149 | Expired |
| US6535423B2 | Drain bias for non-volatile memory | Physics | 70 | Expired |
| US6097637A | Dynamic single bit per cell to multiple bit per cell memory | Physics | 69 | Expired |
| US5444656A | Apparatus for fast internal reference cell trimming | Physics | 64 | Expired |
| US5828616A | Sensing scheme for flash memory with multilevel cells | Physics | 52 | Expired |
| US5438546A | Programmable redundancy scheme suitable for single-bit state and multibit state nonvolatile memories | Physics | 51 | Expired |
| US5754566A | Method and apparatus for correcting a multilevel cell memory by using interleaving | Physics | 44 | Expired |
| US5663923A | Nonvolatile memory blocking architecture | Physics | 42 | Expired |
| US5748546A | Sensing scheme for flash memory with multilevel cells | Physics | 42 | Expired |
| US5497354A | Bit map addressing schemes for flash memory | Physics | 41 | Expired |
| US5046046A | Redundancy CAM using word line from memory | Physics | 36 | Expired |
| US5801991A | Deselected word line that floats during MLC programming of a flash memory | Physics | 33 | Expired |
| US6483742B1 | Bit map addressing schemes for flash memory | Physics | 22 | Expired |
| US5796667A | Bit map addressing schemes for flash memory | Physics | 21 | Expired |
| US5047989A | Chapter mode selection apparatus for MOS memory | Physics | 21 | Expired |
| US5394037A | Sense amplifiers and sensing methods | Electricity | 21 | Expired |
| US5781472A | Bit map addressing schemes for flash/memory | Physics | 19 | Expired |
| US6434049B1 | Sample and hold voltage reference source | Physics | 14 | Expired |
| US6772273B1 | Block-level read while write method and apparatus | Physics | 14 | Expired |
| US5274278A | High-speed tri-level decoder with dual-voltage isolation | Electricity | 14 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.