Method of manufacturing semiconductor memory device
US5049516A · kind A · utility
62Cited by
6References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 15, 1989 |
| Grant date | Sep 17, 1991 |
| Priority date | — |
| Expiry date | Dec 15, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An EEPROM formed of three-layer polysilicon is provided. A floating gate is at a second level and a portion thereof is at a first level. A first control gate and a select gate are formed spaced against from each other at the first level and a portion of the second floating gate extends between them for formation of a tunnel region. A second control gate which is kept at the same potential as the first control gate exist at a third level. In this EEPROM, electrons are drawn from the floating gate by applying a high voltage to the select gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.