Apparatus with a single memory and a plurality of queue counters for queuing requests and replies on a pipelined packet bus
US5050066A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1988 |
| Grant date | Sep 17, 1991 |
| Priority date | — |
| Expiry date | Oct 14, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for queuing requests and replies on a pipelined packet bus. A RAM (212) buffers bus requests by storing packet information corresponding to each request to be sent over said bus in bus time slots allotted to each request. Three send slots (208) keep track of the state of three send requests that are stored in the RAM (212). Three receive slots (210) keep track of the state of three receive requests that are stored in the RAM (212). Nine send queue counters (230) are stepped through a series of states to track an outgoing request and to track a corresponding incoming reply. Six receive queue counters (232) are stepped through a series of states to track an incoming request and to track a corresponding reply. An output MUX (214) connected to the send and receive queues generates status information as to the state of the slots. The status information as to the state of the send and receive slots is used to control the incrementing or decrementing of the send queue counters (230) and the receive queue counters (232 ) in accordance with a predetermined system bus protocol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.