Method and apparatus for using extracted program flow information to prepare for execution multiple instruction streams
US5050068A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1988 |
| Grant date | Sep 17, 1991 |
| Priority date | — |
| Expiry date | Oct 3, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3822
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A prefetching replicated instruction stream machine (PRISM) computer architecture which provides sustained instruction stream performance comparable to peak performance in computer systems with instruction pipelines operates by partitioning, prior to execution, a computer program to be executed into instruction segments based on entry point and branch target instructions defining the flow changes within the program; storing selected segments in a plurality of instruction decoding units (IDUs) such that all instructions that potentially could be needed when the next instruction is executed by a central processing unit (CPU) are stored in the IDUs, and such that no single IDU contains both a segment having a branch taken instruction and a segment containing a branch not taken instruction for the same branch instruction; simultaneously decoding in a predetermined order the instruction segments stored in each IDU; and selectively communicating instructions decoded by the IDUs to the CPU in response to the value of a program instruction counter value identifying the instruction to be executed by the CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.