Robert F. Krick
34Patents
15h-index
34Co-inventors
81Inventor score
Filing activity: Oct 3, 1988 → Dec 5, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6018786A | Trace based instruction caching | Physics | 77 | Expired |
| US5781774A | Processor having operating modes for an upgradeable multiprocessor computer system | Physics | 69 | Expired |
| US5050068A | Method and apparatus for using extracted program flow information to prepare for execution multiple instruction streams | Physics | 65 | Expired |
| US6442674B1 | Method and system for bypassing a fill buffer located along a first instruction path | Physics | 62 | Expired |
| US6014742A | Trace branch prediction unit | Physics | 56 | Expired |
| US6170038A | Trace based instruction caching | Physics | 41 | Expired |
| US5630107A | System for loading PLL from bus fraction register when bus fraction register is in either first or second state and bus unit not busy | Physics | 40 | Expired |
| US7856633B1 | LRU cache replacement for a partitioned set associative cache | Physics | 30 | Expired |
| US5490279A | Method and apparatus for operating a single CPU computer system as a multiprocessor system | Physics | 29 | Expired |
| US5726921A | Floating point power conservation | Physics | 22 | Expired |
| US5638382A | Built-in self test function for a processor including intermediate test results | Physics | 21 | Expired |
| US6493797B1 | Multi-tag system and method for cache read/write | Emerging Cross-Sectional Technologies | 20 | Expired |
| US6457119B1 | Processor instruction pipeline with error detection scheme | Physics | 17 | Expired |
| US6578138B1 | System and method for unrolling loops in a trace cache | Physics | 16 | Expired |
| US6338132B1 | System and method for storing immediate data | Physics | 15 | Expired |
| US6009504A | Apparatus and method for storing data associated with multiple addresses in a storage element using a base address and a mask | Physics | 13 | Expired |
| US6493821B1 | Recovery from writeback stage event signal or micro-branch misprediction using instruction sequence number indexed state information table | Physics | 11 | Expired |
| US5884091A | Computer system having a central processing unit responsive to the identity of an upgrade processor | Physics | 10 | Expired |
| US6035315A | Floating point power conservation | Physics | 8 | Expired |
| US9058269B2 | Method and apparatus including a probe filter for shared caches utilizing inclusion bits and a victim probe bit | Physics | 7 | Active |
| US6915396B2 | Fast priority determination circuit with rotating priority | Physics | 6 | Expired |
| US5931930A | Processor that indicates system bus ownership in an upgradable multiprocessor computer system | Physics | 4 | Expired |
| US6711669B2 | System and method for storing immediate data | Physics | 3 | Expired |
| US6918021B2 | System of and method for flow control within a tag pipeline | Physics | 3 | Expired |
| US7149883B1 | Method and apparatus selectively to advance a write pointer for a queue based on the indicated validity or invalidity of an instruction stored within the queue | Physics | 2 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.