Semiconductor memory device
US5051954A · kind A · utility
29Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 11, 1989 |
| Grant date | Sep 24, 1991 |
| Priority date | — |
| Expiry date | Sep 11, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory cells disposed in a matrix are divided into a plurality of blocks. Each block is constructed of n (n is a positive integer larger than 2) memory cell columns. One block is selected by one column address. One memory cell column in the n memory cell columns in a selected block is selected by a first gate. One memory cell column in the n memory cell colunns in a selected block is selected by a second gate. One memory cell in a selected memory cell column is selected by a row address. The data in a selected memory cell are stored in a register and output therefrom.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.