Method of manufacturing a bipolar transistor
US5055419A · kind A · utility
12Cited by
4References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 17, 1988 |
| Grant date | Oct 8, 1991 |
| Priority date | — |
| Expiry date | May 17, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/124
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p.sup.+ base contact (12) is achieved by using oxidized sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p.sup.+ base contact implantation mask. Collector contact (13) alignment can be achieved using oxidized sidewalls (17) of polycrystalline silicon alignment mesas (14) defined in the same polysilicon as the emitter mesa (7) but deposited on oxide (2) rather than the implanted base region (5).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.