Process for fabricating semiconductor integrated circuit devices
US5055420A · kind A · utility
3Cited by
15References
37Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 9, 1989 |
| Grant date | Oct 8, 1991 |
| Priority date | — |
| Expiry date | May 9, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
Abstract
After contact holes for the P- and N-type source or drain regions of P- and N-channel MOSFETs have been made at a common step, an N-type impurity is ion-implanted into at least the N-type source or drain regions through the contact holes. The N-type impurity is annealed to fornm an N-type region which is deeper than the N-type source or drain regions. During the annealing treatment, the N-type source or drain regions are covered with an insulating film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.