Via capacitors within multi-layer, 3 dimensional structures/substrates
US5055966A · kind A · utility
53Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1990 |
| Grant date | Oct 8, 1991 |
| Priority date | — |
| Expiry date | Dec 17, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/928
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A capacitor structure in a hybrid multilayer circuit having a plurality of insulating layers, the capacitor structure including a dielectric via fill in a via formed in one of the insulating layers, a first conductive element overlying the dielectric via fill, and a second conductive element underlying said dielectric via fill. Each of the first and conductive elements comprises a conductive via fill or a conductive trace.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.