System scan path architecture
US5056093A · kind A · utility
99Cited by
3References
41Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 9, 1989 |
| Grant date | Oct 8, 1991 |
| Priority date | — |
| Expiry date | Aug 9, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system scan path architecture is provided by a device select module (DSM) (18) which may be used in conjunction with associated circuits (16a-b) to select secondary scan paths (PATH1-m) on each circuit for coupling with a primary scan path on a test bus (14). The test bus (14) is controlled by a primary bus master (12). Remote bus masters (124) may be used in conjunction with the DSMs (18) to provide serial-scan testing independent of the primary bus master (12).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.