Delay fault testing method and apparatus
US5056094A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 9, 1989 |
| Grant date | Oct 8, 1991 |
| Priority date | — |
| Expiry date | Jun 9, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31858
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously. This architecture allows propagation delays between devices to be determined. A driving device (264) toggles its input on a first clock edge. On a subsequent clock edge, the receiving circuit (266) samples its input. The sampled input may be scanned out and compared to the toggled value to determine whether the signal propagated between the first and second clock edges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.