Formation of integrated circuit electrodes
US5057455A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1989 |
| Grant date | Oct 15, 1991 |
| Priority date | — |
| Expiry date | Nov 30, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/97
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the fabrication of electrodes for transistors in the BiCMOS integrated circuit, vertical windows etched in a relatively thick TEOS (or other suitable dielectric) layer, located on a relatively thin polysilicon layer, in turn located on relatively tin oxide layer areas and on relatively thick oxide layer areas, are used to define areas where polysilicon electrode material is to remain. Polysilicon is deposited in the windows in the relatively thick insulating layer, to form the basis for the desired electrode in each window. The relatively thin polysilicon layer (or, alternatively an .alpha.-amorphous silicon layer) is thereafter used as an etch stop during the subsequent removal of the relatively thick dielectric layer. Thereafter both MOS and bipolar transistors can be fabricated using the windows to define the extents of the gate regions of the MOS transistors and the extents of the emitter regions of the bipolar transistors. In addition, both the source and drain electrodes of the MOS transistors and the base electrodes of the bipolar transistors can then be simultaneously formed in a self-aligned manner without the need for etching into the underlying semiconductor substrate…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.