Logic level shifting circuit with minimal delay
US5059829A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 1990 |
| Grant date | Oct 22, 1991 |
| Priority date | — |
| Expiry date | Sep 4, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/017527
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit enabling the conversion of a set of ECL and a set of CMOS logic levels has a differential amplifier, two emitter followers, a current switching circuit, and a level shifting circuit. The differential amplifier provides a common mode input to two emitter followers which switch very rapidly using ECL voltage levels. High operational speed is accomplished by providing a relaxation current during logic high-to-low voltage transients. The current switching circuit conserves power consumption by switching off the relaxation current during logic low-to-high transients, during which time the emitter followers switch sufficiently fast. The level shifting circuit converts the set of ECL logic voltage levels to a set of CMOS voltage levels and the CMOS output voltage is used to control the current switching circuit without introducing a switching delay time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.