Method of manufacturing a semiconductor device structure employing a multi-level epitaxial structure
US5061652A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 1990 |
| Grant date | Oct 29, 1991 |
| Priority date | — |
| Expiry date | Jan 23, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure including a doped semiconductor substrate defining a surface. A buffer layer of epitaxial semiconductor material overlies the substrate surface, the buffer layer having a relatively higher dopant concentration than the substrate and being virtually free from oxygen precipitation. A layer of intrinsic semiconductor material overlies the buffer layer, and a device layer of epitaxial semiconductor material is situated on the intrinsic layer. The device layer is formed to have a relatively lower dopant concentration than the first layer. Isolation regions extend from a surface of the device layer into the buffer layer for forming an electrically isolated device region in the device layer. At least one active device is formed in the isolated device region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.