"Method for testing integrated circuits having a grid-based, ""cross-check"" t e"
US5065090A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 13, 1988 |
| Grant date | Nov 12, 1991 |
| Priority date | — |
| Expiry date | Jul 13, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new test structure is described which allows full testing of highly complex Integrated Circuits. The test structure consists of a grid of externally as well as individually accessible probe-lines and sense-lines with electronic switches at the crossings of said probe and the sense-lines. One end of the switches is tied to an array of test-points on the IC that are to be either monitored or controlled during the testing, and the other end of the switches is tied to a sense-line. The ON and the OFF states of the switches are controlled by probe-lines. The probe and sense lines are connected to test electronics, thus permitting the test electronics to control the electrical signals on the probe-lines and to measure or apply signals on the sense-lines. Thus, by the excitation of an appropriate probe-line and the monitoring of an appropriate sense-line, the test signals present at any one of the test-points can be measured. Conversely, by the excitation of an appropriate probe-line and application of a test signal on another appropriate sense-line the electrical signal on any of the test-points can be externally controlled for the purpose of testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.