Amorphous silicon thin film transistor array substrate and method for producing the same
US5065202A · kind A · utility
8Cited by
8References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1990 |
| Grant date | Nov 12, 1991 |
| Priority date | — |
| Expiry date | Jun 4, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/443
Abstract
An amorphous silicon thin film transistor array substrate is formed on an insulating substrate with a gate insulating layer, as gate wiring itnerconnecting gate electrodes and source wiring interconnecting source electrodes. The gate insulating layer is provided in a lower layer of a terminal part of the source wiring. In the process for forming the array, the gate insulating layer is formed in a portion of the structure other than the terminal part of the gate, and the terminal part of the source wiring is formed on the gate insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.