Three dimensional packaging arrangement for computer systems and the like
US5065277A · kind A · utility
93Cited by
3References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 13, 1990 |
| Grant date | Nov 12, 1991 |
| Priority date | — |
| Expiry date | Jul 13, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K7/023
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A three dimensional arrangement for packaging planar arrays of circuit components in a plurality of essentially planar layers in which the layers lie closely adjacent to one another is disclosed. Each layer is separated by a shell that interposes slots for allowing coolant to pass between the layers and electrical conductors through the shell, so that when the layers are placed together, the conductors form a bus through the structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.