Video RAM double buffer select control
US5065368A · kind A · utility
24Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 1989 |
| Grant date | Nov 12, 1991 |
| Priority date | — |
| Expiry date | May 16, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An implementation of a serial access memory register that facilitates the selecting from two alternate frame buffers on a per pixel basis. The frame buffers are each stored in a portion of a row in a single video RAM. Following data transfer to the serial access memory register, data from each of the two frame buffers is available. A double buffer select signal controls the selection of which half of the serial access memory register will put data on the output bus for each serial clock signal. The serial clock increments the address pointers in both halves of the serial access memory port simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.