System and method for automatically configuring translation of logical addresses to a physical memory address in a computer memory system
US5067105A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 1987 |
| Grant date | Nov 19, 1991 |
| Priority date | — |
| Expiry date | Nov 16, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for altering physical addresses of semiconductor memory cards to locate an error-free portion to provide a contiguous range of storage which is free from errors. The system contains a memory card ID register which stores the physical addresses of memory cards in positions corresponding to logical addresses. The system evaluates the results of routine tests of memory and rearranges the physical addresses stored in the memory card ID register to provide an error-free portion at the desired logical address range. A separate memory configuration register stores a value representing the size of the memory cards. The value stored in the memory configuration register selects a subset of the logical memory address bits to obtain a logical card address. The logical card address selects a position in the memory card ID register to obtain the physical address of the memory card.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.