Single transistor non-volatile electrically alterable semiconductor memory device with a re-crystallized floating gate

US5067108A · kind A · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventor

• Ching-Shi Jenq · Los Altos Hills, US

Key dates

• Filing date: Jan 22, 1990
• Grant date: Nov 19, 1991
• Expiry date: Jan 22, 2010

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6891

Abstract

A single transistor electrically programmable and erasable memory cell has a substrate of a semiconductor material of a first-conductivity type. Within the substrate are defined source and drain, regions with a channel region therebetween. A first insulating layer is disposed over the substrate and over the source, channel and drain regions. An electrically conductive, re-crystallized floating gate is disposed over the first-insulating layer and extends over a portion of the channel region and over a portion of the drain region to maximize capacitive coupling therewith. A second insulating layer has a top wall portion over the floating gate and a side wall portion immediately adjacent to the floating gate and has a thickness which permits the Fowler-Nordheim tunneling of charges therethrough. An electrically conductive control gate has two electrically connected sections: A first section is over the first insulating layer and is immediately adjacent to the side-wall portion of the second insulating layer. The first section extends over a portion of the channel region and over the source region. A second section is disposed over the top wall portion of the second insulating layer to…