Method of manufacturing DRAM cell
US5068200A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 1990 |
| Grant date | Nov 26, 1991 |
| Priority date | — |
| Expiry date | Mar 8, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
Abstract
This invention relates to a method of manufacturing a DRAM cell which has a stacked capacitor and forming drain and source polycrystalline silicon regions on surface of a semiconductor substrate. The invention is directed to: a first step for forming a field oxide film and channel stopper as well as a polycrystalline silicon oxide film doped with impurities; a second step for dividing said silicon into a drain and source polycrystalline silicon region and forming a gate oxide film between the two silicon regions simultaneously with the drain and source diffusion regions and a gate electrode on the gate nitride film; a third step for forming an insulating film on the upper surface of the nitride film and a window on the source polycrystalline silicon region, a storage poly contacting with the same through the window; a fourth step for forming a dielectric layer and a plate poly of the stacked capacitor; and a fifth step forming another insulating film thereon and forming a window on the drain polycrystalline silicon region and also forming a bit line contacting with the exposed drain polycrystalline silicon region through that window. This invention can prevent the generation of lea…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.