Laegu Kang
19Patents
6h-index
40Co-inventors
66Inventor score
Filing activity: Mar 8, 1990 → Oct 24, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6724048B2 | Body-tied silicon on insulator semiconductor device and method therefor | Electricity | 22 | Expired |
| US6620656B2 | Method of forming body-tied silicon on insulator semiconductor device | Electricity | 18 | Expired |
| US8809178B2 | Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currents | Electricity | 12 | Active |
| US7186596B2 | Vertical diode formation in SOI application | Electricity | 8 | Expired |
| US5068200A | Method of manufacturing DRAM cell | Electricity | 7 | Expired |
| US8445969B2 | High pressure deuterium treatment for semiconductor/high-K insulator interface | Electricity | 7 | Active |
| US7528078B2 | Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer | Electricity | 6 | Active |
| US9099525B2 | Blanket EPI super steep retrograde well formation without Si recess | Electricity | 3 | Active |
| US8790972B2 | Methods of forming CMOS transistors using tensile stress layers and hydrogen plasma treatment | Electricity | 2 | Active |
| US8916442B2 | Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device | Electricity | 1 | Active |
| US7126172B2 | Integration of multiple gate dielectrics by surface protection | Electricity | 1 | Expired |
| US7517742B2 | Area diode formation in SOI application | Electricity | 1 | Active |
| US8106462B2 | Balancing NFET and PFET performance using straining layers | Electricity | 0 | Active |
| US10483172B2 | Transistor device structures with retrograde wells in CMOS applications | Electricity | 0 | Active |
| US9852954B2 | Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures | Electricity | 0 | Active |
| US9209181B2 | Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures | Electricity | 0 | Active |
| US7795089B2 | Forming a semiconductor device having epitaxially grown source and drain regions | Electricity | 0 | Active |
| US9362357B2 | Blanket EPI super steep retrograde well formation without Si recess | Electricity | 0 | Active |
| US9099380B2 | Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.