Memory cell circuit and operation thereof
US5068825A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1990 |
| Grant date | Nov 26, 1991 |
| Priority date | — |
| Expiry date | Jun 29, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved memory cell 118 is provided utilizing transistor pairs 142, 144 ands 160, 162 as dual purpose transistor pairs for the two modes of operation of the cell. During the first or non-access mode of operation, the transistor pairs operate as switched capacitive elements in order to provide an equivalent resistance between bit line 140 and first node 26 and inverted bit line 158 and second node 130. Control circuit 119 maintains bit lines 140 and inverted bit line 158 high during this non-access mode. During the second or access mode of operation, each transistor pair operates as a respective pass transistor for connecting bit line 140 to first node 126 and inverted bit line 158 to second node 130 so that data may be read from, or written to, the cross-coupled transistors 120 and 122.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.