Semiconductor memory device having memory cells including IG FETs in a symmetrical arrangement
US5072286A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 1990 |
| Grant date | Dec 10, 1991 |
| Priority date | — |
| Expiry date | Sep 25, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
A semiconductor memory device has memory cells each including first and second inverters cross-coupled to each other through first and second interconnecting conductors for forming a bistable circuit and first and second transfer gates connected between the first inverter and address signal conductors and between the second inverter and the address signal conductors, respectively. The first and second interconnecting conductors are arranged substantially point-symmetrically and have at least portions substantially parallel with each other on a surface of a substrate, and IG FETs constituting the first and second inverters have their gate electrodes arranged substantially parallel with one another and extending in a direction substantially perpendicular to the parallel portions of the first and second interconnecting conductors for the cross-coupling on the surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.