Method of making DRAM having a side wall doped trench and stacked capacitor structure
US5075248A · kind A · utility
24Cited by
10References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 1991 |
| Grant date | Dec 24, 1991 |
| Priority date | — |
| Expiry date | Feb 20, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/047
Abstract
A DRAM cell having a SDTAS structure having a trench stacked capacitor which includes a capacitor charge storage electrode which is in physical contact and is electrically connected to a N+ drain region, and a VCC/2 electrode which is electrically isolated by an ONO layer formed between the capacitor charge storage electrode and the VCC/2 electrode is disclosed. Such cell can increase the capacitance of the capacitor and reduce the area of the cell by reducing the width of the MOSFET, and a method for manufacturing such cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.