Electrically erasable programmable read-only memory with NAND cell
US5075890A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1990 |
| Grant date | Dec 24, 1991 |
| Priority date | — |
| Expiry date | Apr 30, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically erasable programmable read-only memory has memory cell blocks, each of which has NAND type cell units associated with the bit lines respectively. Each cell unit has a series-circuit of floating gate type memory cell transistors and a selection transistor provided between the corresponding bit line and the series-circuit of memory cell transistors. A row decoder is provided in common to the memory cell blocks, for generating an "H" level voltage which is supplied to a selection gate control line connected to the selection transistor and to a selected word line or lines in a cell unit. A voltage boost circuit is provided for every memory cell block, for causing the "H" level voltage to increase up to a preselected potential level which is high enough to render the cell transistors conductive. The voltage boost circuit includes a first booster section for the selection gate control line, and a second section for the word lines. The second section operates in response to the output voltage of the first section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.