Method for improving erase characteristics of buried bit line flash EPROM devices by use of a thin nitride layer formed during field oxide growth
US5077230A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 1990 |
| Grant date | Dec 31, 1991 |
| Priority date | — |
| Expiry date | Aug 3, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/114
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The cells use elongated source and drain regions disposed beneath field oxide regions. Ammonia formed during the field oxidation process reacts with the silicon substrate to form a thin silicon nitride layer in the beak region. A thin tunnel oxide is then grown. During tunnel oxide formation lateral growth of the field oxide is inhibited by the thin nitride layer previously formed. However, the tunnel oxide thinning (due to the existence of the thin nitride layer) induced low breakdown voltage is overcome by the enhanced oxide growth in the beak due to the buried source/drain dopants. The tunnel oxide in the erase region is therefore uniform and thin. The thin, uniform oxide in the tunnel region leads to improved erase characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.