Been-Jon Woo
17Patents
12h-index
12Co-inventors
75Inventor score
Filing activity: Nov 4, 1986 → Dec 18, 2007
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US4728617A | Method of fabricating a MOSFET with graded source and drain regions | Emerging Cross-Sectional Technologies | 90 | Expired |
| US5210047A | Process for fabricating a flash EPROM having reduced cell size | Emerging Cross-Sectional Technologies | 83 | Expired |
| US5075245A | Method for improving erase characteristics of buried bit line flash EPROM devices without using sacrificial oxide growth and removal steps | Emerging Cross-Sectional Technologies | 72 | Expired |
| US4757026A | Source drain doping technique | Emerging Cross-Sectional Technologies | 46 | Expired |
| US5229631A | Erase performance improvement via dual floating gate processing | Electricity | 37 | Expired |
| US5147813A | Erase performance improvement via dual floating gate processing | Emerging Cross-Sectional Technologies | 35 | Expired |
| US5102814A | Method for improving device scalability of buried bit line flash EPROM devices having short reoxidation beaks and shallower junctions | Electricity | 31 | Expired |
| US5470772A | Silicidation method for contactless EPROM related devices | Electricity | 28 | Expired |
| US4784965A | Source drain doping technique | Emerging Cross-Sectional Technologies | 28 | Expired |
| US4833099A | Tungsten-silicide reoxidation process including annealing in pure nitrogen and subsequent oxidation in oxygen | Emerging Cross-Sectional Technologies | 25 | Expired |
| US5077230A | Method for improving erase characteristics of buried bit line flash EPROM devices by use of a thin nitride layer formed during field oxide growth | Emerging Cross-Sectional Technologies | 23 | Expired |
| US4774201A | Tungsten-silicide reoxidation technique using a CVD oxide cap | Emerging Cross-Sectional Technologies | 16 | Expired |
| US7465625B2 | Flash memory cell having reduced floating gate to floating gate coupling | Electricity | 9 | Active |
| US5196361A | Method of making source junction breakdown for devices with source-side erasing | Electricity | 7 | Expired |
| US7348618B2 | Flash memory cell having reduced floating gate to floating gate coupling | Electricity | 5 | Expired |
| US7015149B2 | Simplified dual damascene process | Electricity | 2 | Expired |
| US7632736B2 | Self-aligned contact formation utilizing sacrificial polysilicon | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.