Reducing clock skew in large-scale integrated circuits
US5077676A · kind A · utility
58Cited by
5References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1990 |
| Grant date | Dec 31, 1991 |
| Priority date | — |
| Expiry date | Mar 30, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a system of digital chips, the time delay in all clock trees is equalized by equalizing the delay through each level of all trees. The level delays are equalized by adjusting the capacitance of terminators in each net at each level, and/or by adjusting the performance (power) of each driver at each level. Where the capacitance of a net is too low to be compensated by a driver, a capacitive terminator is selectively added to that net.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.