Semiconductor memory device
US5079603A · kind A · utility
38Cited by
10References
52Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1990 |
| Grant date | Jan 7, 1992 |
| Priority date | — |
| Expiry date | Apr 30, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
Abstract
This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.