Process to fabricate a double ring stacked cell structure
US5084405A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1991 |
| Grant date | Jan 28, 1992 |
| Priority date | — |
| Expiry date | Jun 7, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/043
Abstract
An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to as a Double Ring Stacked Cell or DRSC. The DRSC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The DRSC is made up of a polysilicon storage node structure having circular polysilicon ringed upper portion centered about a lower portion that makes contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed DRSC capacitor. The novel 3-dimensional shaped polysilicon storage node plate having double polysilicon rings, allows substantial capacitor plate surface area of 200% or more to be gained at the storage node over that of a conventional STC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.