Packaging for multiple chips on a single leadframe
US5084753A · kind A · utility
35Cited by
11References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 23, 1989 |
| Grant date | Jan 28, 1992 |
| Priority date | — |
| Expiry date | Jan 23, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/07802
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The foregoing objects are achieved in an assembly wherein the die attach paddle of a conventional leadframe is cut to form two electrically isolated die attach paddles and a dielectric tape is applied to one side of the two die attach paddles, spanning the space between them, providing physical support and substantially preventing cantilevered or twisting motion of the die attach paddles relative to the remainder of the leadframe assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.