Synchronizing circuit of two clock signals
US5086236A · kind A · utility
17Cited by
5References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 27, 1990 |
| Grant date | Feb 4, 1992 |
| Priority date | — |
| Expiry date | Aug 27, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1515
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is disclosed a synchronizing circuit for synchronizing a first clock signal to a second clock signal. The synchronizing circuit includes an edge-triggered set-reset latch and a delay circuit. A subclock generator generates first and second subclock signals from a synchronizing clock to control the delay circuit so that the synchronized signal at the output of the circuit is exactly one full cycle period of the synchronizing clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.