Semiconductor device having latch means
US5086414A · kind A · utility
13Cited by
2References
29Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Nov 15, 1989 |
| Grant date | Feb 4, 1992 |
| Priority date | — |
| Expiry date | Nov 15, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor circuit having a plurality of circuit blocks, each having latch circuits each one thereof being controlled by an internally provided clock signal for preventing malfunction of the circuit. Each circuit is provided with the latch function so that the cycle time is made shorter than the access time. Moreover, the latch means are driven in such a manner that the adjoining ones are prevented from being put to through-state simultaneously, whereby malfunction is prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.