Redundancy decoding circuit using n-channel transistors
US5088066A · kind A · utility
18Cited by
10References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 10, 1989 |
| Grant date | Feb 11, 1992 |
| Priority date | — |
| Expiry date | Feb 10, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Four n-channel transistor, single-stage XNOR/XOR decoding circuit provides for an improved performance of a decoding circuit using CAMs to access redundant memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.