Process for producing optimum intrinsic, long channel, and short channel MOS devices in VLSI structures

US5091324A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• James Hsu · Cincinnati, US
• Yowjuang W. Liu · San Jose, US

Key dates

• Filing date: Aug 10, 1990
• Grant date: Feb 25, 1992
• Expiry date: Aug 10, 2010

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/082

Abstract

Highly doped short channel NMOS devices with punch-through protection; intrinsic NMOS devices with low threshold voltage; and long channel NMOS and PMOS devices with low body factor; are constructed by providing one or more lightly doped P regions in a semiconductor wafer in which intrinsic and long channel NMOS devices may be constructed, and one or more N wells in the wafer where PMOS devices can be constructed; forming isolation oxide on the wafer before implanting the wafer to inhibit field inversion in N channel (NMOS) devices; masking N regions of the wafer except where long channel PMOS devices will be formed and portions of P regions of the wafer where long channel NMOS devices will be constructed, and optionally masking P regions where either intrinsic NMOS devices or short channel NMOS devices will be formed; and then implanting the wafer to simultaneously provide a field implant below the isolation oxide, adjacent regions where NMOS devices will be formed, as well as optionally providing a deep implant in P regions where short channel NMOS devices will be constructed to provide punchthrough protection, and optionally providing a deep implant in P regions where intrinsic …